Communication common carriers are actively promoting the building of high-speed data communication networks with a view to realize higher value-added services.
A high-speed data communication network requires a large traffic capacity. For such a network, an Internet Protocol (IP) approach is more suitable than a time-division multiplex approach because the former is sufficiently efficient and is less costly than the latter.
However, once a network shifts to an IP approach, it becomes essential for some applications to communicate highly accurate clock information to devices that are connected to the packet network.
For example, in order to achieve high-quality exchange of real-time audio and/or video data between a transmitter and receiver, the data must be reproduced at pre-determined timings. This requirement cannot be met without a stable clock.
In a mobile network as well, an accurate clock is essential in order to reliably achieve inter-cell handover.
More specifically, base stations within a mobile network are required to synchronize among one another at an accuracy of 50 ppb (parts per billion). If the clock in a base station drifts beyond this limit, an inter-cell handover in which the base station is involved would fail, very often resulting in packet losses and/or deteriorated communication quality.
Thus, in order to achieve a stable service quality, a method is necessary that can communicate accurate clock information over a packet network. One technology that is effective in solving the above-described problem is the timestamp approach. A timestamp mechanism is easy to implement and can achieve a high level of clock synchronization accuracy.
FIG. 14 shows an example system structure based on the timestamp approach described above. In the timestamp approach, clock synchronization is ensured by causing the master node to transmit a timestamped packet to the slave node and the slave node to adjust its clock according to the timestamp.
More specifically, a timestamp is used to generate a control signal for a phase synchronization loop (PLL). The PLL achieves clock synchronization by calculating a difference between its clock and the timestamp that has newly arrived and adjusting its clock based on the difference.
The PLL circuit 300 shown in FIG. 14 primarily consists of six different functions. These functions are a phase comparison part 301, loop filter (LPF) part 302, a proportion/integral (PI) control part 303, a voltage control oscillation part (VCO) 304, a frequency division part 305, and a timestamp generation part 306.
The phase comparison part 301 calculates a differential signal between the received timestamp and the timestamp generated by the slave node. The differential signal is inputted into the LPF part 302 to suppress the jitters and noises therein.
The PI control part 303 outputs to the VCO part 304 a control signal configured to ultimately reduce the differential signal to zero.
The VCO part 304 outputs a clock with a frequency to be determined by the control signal from the PI control part 303.
The frequency division part 305 generates an up-converted or down-converted clock by converting the frequency received from the VCO part 304.
The timestamp generation part 306 outputs a timestamp based on the received clock.
Arts based on the above-described timestamp approach are disclosed in, for example, Patent Literature 1 and Patent Literature 2.    Patent Literature 1: Japanese Patent Laying-Open No. Hei 05-37560.    Patent Literature 2: Japanese Patent Laying-Open No. 2003-258894.
A clock synchronous state as used herein is a state in which the timing of the received timestamp 400 completely matches that of the timestamp 401 generated by the slave, node, as shown in FIG. 15(A).
On the other hand, in a state in which the two clocks are not synchronous (i.e., an “asynchronous state”), as shown in FIG. 16(B), there exists a deviation in timing between the timestamp 400 and the timestamp 401.
In order to achieve highly accurate clock synchronization, it is necessary to quickly detect such a deviation and correct the clock timing. However, a deviation may not easily be detected, depending on the way the two timestamps deviate from each other.
FIG. 16 shows an example of such a situation. First, a case where the clock frequency on the slave node side is lower than that on the master node side will be considered.
The timestamp on the slave node side, which is represented by the pattern in the middle line in FIG. 16, is progressing more slowly than that on the master node side. The deviation between the timestamps of the master and slave nodes can be detected by checking the second timestamp.
Next, a case where the slave-node clock frequency is higher than the master-node clock frequency will be considered.
The slave-node timestamp, which is represented by the pattern in the lower line in FIG. 16, is progressing faster than the master-node timestamp. In this case, the deviation between the timestamps of the master and slave nodes cannot be detected until the eighth timestamp is reached.
In situations like the latter case, clock synchronization accuracy deteriorates because a deviation between timestamps cannot be detected quickly and it therefore takes a longer time to correct clock frequency.